Generally, a semiconductor memory device starts its operation after a power voltage level rises up to a certain level instead of starting in response to the level of the power voltage immediately after the power voltage is externally supplied. For this reason, the semiconductor memory device usually includes a power-up circuit.
The power-up circuit prohibits the entire memory device from damaged due to latch-up when the internal circuit of the device is operated before the power voltage is stabilized after the power voltage is supplied externally so that chip level reliability can be improved. Such a power-up circuit detects the rise of the power voltage that is supplied externally when the power voltage is supplied initially so as to output a power-up signal in ‘low’ state till a certain level of the power voltage and then make a transition of the power-up signal to ‘high’ state after the power voltage is stabilized over the certain level. On the contrary, when the power voltage falls, the power-up circuit outputs the power-up signal in ‘high’ state till the certain level of the power voltage and then outputs the power-up signal in ‘low’ state again after the power voltage level falls down under the certain level. The power-up signal is outputted as ‘high’ after the power voltage is stabilized and operated independently in a unit of pipe within the memory inner circuit to be used mostly for circuits which require initialization operation.
FIG. 1 is a circuit diagram of a power-up signal generating apparatus in prior art.
Referring to FIG. 1, the power-up signal generating apparatus comprises a bias signal generating unit 10 for generating a bias signal bias, a sensing level adjusting unit 11 for sensing rising of a power supply voltage VDD to adjust an voltage level of an output node ND2, and an output signal forming unit 12 for outputting the voltage on the output node ND2 as a power-up signal pwrup.
The bias signal generating unit 10 includes a PMOS transistor PM1 having a ground voltage VSS as its gate input and a source-drain path between the power supply voltage VDD and a node ND1, and an NMOS transistor NM1 having a drain coupled to its gate and a drain-source path between the node ND1 and the ground voltage VSS to output the voltage on the node ND1 as the bias signal bias.
When the power supply voltage VDD exceeds the threshold voltage Vt of the NMOS transistor NM1 while rising, the NMOS transistor NM1 is turned on so as to output the bias signal bias having a certain level.
Further, the sensing level adjusting unit 11 includes two serially coupled PMOS transistors PM2, PM3 between the power supply voltage VDD and the output node ND2, each transistor having a drain coupled to the corresponding gate.
The output signal forming unit 12 includes an NMOS transistor NM2 having the bias signal as its gate input and a drain-source path between the output node ND2 and the ground voltage VSS, an inverter I1 for inverting the output node ND2, a PMOS transistor PM4 having the output signal of the inverter I1 as its gate input and a source-drain path between the power supply voltage VDD and the output node ND2, and an inverter I2 for inverting the output of the inverter I1 to output as the power-up signal pwrup
Next, it will be described for the operation of the conventional power-up signal generating apparatus.
First, as the power supply voltage VDD rises up to lead rising of the voltage level on the node ND1, the NMOS transistor NM1 becomes active so that the bias signal generating unit 10 outputs the bias signal bias having a stable level. In turn, the NMOS transistor NM2 having the bias signal bias as its gate input is turned on so that the output node ND2 can has a certain portion of the power supply voltage VDD that is obtained by voltage dividing with the PMOS transistors PM2, PM3 in the sensing level adjusting unit 11 and the voltage level on the output node ND2 rises up due to the rise of the power supply voltage VDD. The inverter 11 inverts the voltage on the output node ND2. Because the PMOS transistor PM4 that has the output of the inverter I1 as its gate input inputs the power supply voltage VDD to the output node ND2 in response to falling of the output of the inverter I1 so as to increase the voltage level on the output node ND2 more rapidly. The inverter I2 inverts the output signal of the inverter I1 to output it as the power-up signal pwrup.
For the reference, the sensing level adjusting unit 11 makes the voltage level on the output node ND2 have the certain portion of the power supply voltage VDD so as to adjust the active point of the power-up signal by varying that amount of the portion. Further, the output signal forming unit 12 forms the power-up signal pwrup by using the inverter chain I1, I2 because the voltage level on the output node ND2 comes from voltage dividing of the power supply voltage VDD.
On the other hand, the conventional power-up signal generating apparatus is sensitive to surrounding temperature around the semiconductor, which will be described as follows.
FIG. 2 shows a waveform diagram for operation of a circuit in FIG. 1, which presents the active point of the power-up signal versus temperature.
First, X axis depicts time and Y axis depicts voltage. The waveform of ‘b’ shows the case when the surrounding temperature around the semiconductor is room temperature, ‘a’ shows the case when the surrounding temperature around the semiconductor is higher than room temperature, and ‘c’ shows the case when the surrounding temperature around the semiconductor is lower than room temperature.
Referring to FIG. 2, it can be seen that the active point of the power-up signal pwrup depends on the surrounding temperature around the semiconductor. That is, in the case of ‘a’ when the surrounding temperature is higher than room temperature, the power-up signal pwrup becomes active at lower voltage level than in the case of ‘b’. On the contrary, in the case of ‘c’, the power-up signal pwrup becomes active at a higher voltage level than in the case of ‘b’.
As the surrounding temperature around the semiconductor rises, the threshold voltage Vt of the MOS transistor becomes lower so that the NMOS transistor NM1 can be turned on before the power supply voltage VDD rises up enough to make the voltage level of the bias signal bias becomes lower. Accordingly, the turn-on resistance of the NMOS transistor NM2 that is controlled by the bias signal bias rises up and, in turn, the voltage on the output node ND2 is increased so that the power-up signal pwrup can be active before the power supply voltage VDD rises up enough.
On the contrary, when the surrounding temperature falls down, the threshold voltage Vt of the NMOS transistor NM1 rises up so that the voltage level of the bias signal bias becomes higher. Accordingly, the turn-on resistance of the NMOS transistor NM2 is reduced and, in turn, the voltage level on the output node ND 2 falls down so that the power-up signal becomes active at higher power supply voltage VDD.
As described above, the conventional power-up signal generating apparatus is so sensitive to the surrounding temperature around the semiconductor, which makes the power-up signal pwrup active at irregular levels of the power supply voltage VDD and, as a result, leads failure of initialization operation of a chip and deterioration of chip reliability.
When the power-up signal becomes active before the power supply voltage VDD rises up to a certain level due to rising of the surrounding temperature, chip initialization is failed. On the other hand, when the activation of the power-up signal is lagged due to falling of the surrounding temperature, the semiconductor device operates abnormally in a low voltage region.
Similarly, such phenomena as described above can be seen in case of process changes.